Table 1: Test Vector Micro-Instructions, UUT Syncronization. Here is the test vector code to do a TX Descriptor Read Table 1: Test Vector Micro-Instructions, UUT Syncronization. Here is the test vector code to do a TX Descriptor Read
1 Wait for STE to issue a PCI request as the Initiator (STE asserts REQn Output Low on vector label Wait_TX_Desc_REQ:).
2 The tester which is now the Target, then gives the STE its GNTn.
3 Wait up to 16 PCI Clocks on vector labled Wait_Memory_Access_1 to Match the actual DUT response with its expected response, which is,
that the STE issues the transmit descriptor base address 0x40000000 on the PCI AD bus,
and the Memory Read command (0x6) on the command bus, and asserts FRAME#
4. Burst read which means it reads more than one D-word This is indicated by the four consecutive DATA cycles in attached capture. A burst is indicated by the master
Holding FRAME# and IRDY low after the initial address pulse the attached capture shows all folder D-Word in the Transmit Descriptor being read
5 Insert dummy turn-around per the Read Transaction waveform
6 Then the Target gives the STE Bus Master its DEVSELn and TRDYn by driving them to logic 0, the STE will then begin
reading the TX Descriptor first of 4 D-Words TDES0 (pointed to by the transmit descriptor address) on the next PCI Klunk.
Note reading means the tester has to drive the TXDES0 own bit MSB 31 Hi.
TRDYn is used to hold off the master until the target is ready. On the next the PCI Clock, the tester provides TXDES1 = 0x62000040
(page 40 of 66)which sets the buffer size. 40= 0100 0000 sets the 2 byte count to 2**6= 64 bytes. 64 bytes/4 bytes per
D-word= Burst Length of 16. On the next PCI Clock TXDES2, which is the TX Buffer Address 0xA0000000, is written into (read by) the STE