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New Developments at At-Spex

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1mm BGA Board Pics

New Board Pic 1   New Board Pic 2
Click Picture for High Res   Click Picture for High Res

 

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light   pretty
Our first 1000+ Pin DUT   Stratix IP1S60 F1020 Device Package Diagram
linktopdf   bottomview
Stratix IP1S60 F1020 Datasheet   Bottom View of 1mm BGA Package

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Altera 1020 Pin BGA

 

schematic   Artwork
DUT Card Schematic   Artwork: Click here for pretty picture
1020 Receptacle   silk screen bottom
1020 Pin Receptacle   Silk screen bottom view
Silk Screen top view  
Silk screen top view  

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FASTtm Universal DUT Card 100/200/267 MHz for use with Emulation Technology-style conversion sockets- SOIC's, TSSOP's, PLCC's, QFN's, BGA's, DIP's

 

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.8 mm pitch DUT Card .8 mm pitch DUT Card Bottom 144bga all layers
.8 mm pitch, 144 pin BGA DUT Card (TOP) featuring 3 mil trace width / spacing.; the DUT is a 1 Gb graphics DDR DRAM
(BOTTOM)
144 BGA Artwork

Double Click the pics for 13 Megapixel high resolution zoom

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FPGA Automatic Test Program Development

Xilinx ISE development software .pad file automaticaly converted to an At-Spex pin to channel .p2c compilable Excel Spreadsheet; this example is an 1148 pin XC4VLX60ff1148 90 nm Virtex 4

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80C51 Family Micro-controller test vectors - Instructions / Mnemonics, Bus & Machine cycles

P89C664 PDF screenshot

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Example Simple Test Program and Datalog

TXT file TS file CBV file Adobe PDF

TI-IDT#2.TXT

Datalog

29FCT52.TS

Test Program Source

29FCT52.cvf

JEDEC Test Vector File

29FCT52.pdf

Datasheet

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